The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved fractional clock-based pulse generator for providing a robust pulse signal for controlling the duty-cycle of a digital pulse width modulator (PWM) circuit.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current power sources, such as a buck-mode, pulse width modulation (PWM) based, DC-DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a synchronous PWM signal to a driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a powered load is coupled. In the illustrated DC-DC converter, the electronic power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE applied to its gate from driver 20, while the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE supplied from driver 20. A common node 35 between the two NFETs is coupled through an inductor 50 to a load reservoir capacitor 60 that is coupled to a reference voltage terminal (GND). The connection 55 between inductor 50 and capacitor 60 serves as an output node 55 from which a desired (regulated) DC output voltage VOUT is applied to a LOAD 65 (coupled to GND).
The output node connection 55 is also fed back to error amplifier circuitry 12 within the controller 10. The error amplifier circuitry is used to regulate the converter""s output DC voltage relative to a reference voltage supply. In addition, the common node 35 between the controllably switched NFETs is coupled (by way of a feedback sense resistor 45) to current-sensing circuitry 15 within the controller 10. In response to the two feedback signals the controller adjusts duty ratio of the PWM signal, as necessary, to maintain the converter""s DC output within a prescribed set of parameters.
The controller 10 of FIG. 1 can be implemented with either analog or digital circuits. The digital implementation is desirable for all the reasons that have historically favored digital signal processing techniques, but there is a penalty. A digital controller produces a quantized PWM pulse width, i.e., the PWM pulse width has an irreducible temporal granularity associated with the finite bit length of the digital implementation. The digital PWM granularity imposes performance limitations on the DC-DC regulator in a manner similar to noise in the analog PWM pulse generation. Electronic circuits and systems that are powered by PWM-based DC-DC converters of the type shown in FIG. 1 require precise DC-DC regulation, and the required precision of regulation is tightening with each successive generation of circuits and systems. Consequently, it is desirable to have high digital resolution (small temporal granularity) of the PWM pulse. Ostensibly, this may be accomplished by operating the digital PWM pulse generator at a clock frequency (the clock driving the digital circuitry and providing the smallest increments of time from which the PWM pulse is constructed) that is some large multiple of the fundamental switching frequency (the PWM pulse repetition frequency).
As a non-limiting example, consider the case of a switching frequency of 1 MHz, a digital clock frequency of 100 MHz, and a nominal PWM duty-cycle of 10%. The digital clock cycle resolution limits the actual duty-cycle to P/100, where P is an integer number of clock cycles that make up a single PWM pulse. This means that the duty-cycle resolution in the vicinity of the nominal value PWM duty-cycle of 10% is +/xe2x88x921%, namely 9% or 11%. In either case the actual digital duty-cycle granularity is very coarse, +/xe2x88x9210% of the nominal value PWM duty-cycle.
One way to improve upon this relatively coarse digital resolution is to increase the ratio of the clock signal frequency to the switching frequencyxe2x80x94either by decreasing the switching frequency and/or increasing the frequency of the clock signal. In the above example, a finer granularity/resolution on the order of 0.1% of the switching frequency could be obtained by decreasing the switching frequency to 100 KHz (while maintaining the clock frequency at 100 MHz), or increasing the clock frequency to 1 GHz (while maintaining the switching frequency at 1 MHz). Unfortunately, both choices obviously result in impractical solutions in light of other system requirements and limitations.
A more practical way is to employ a tapped delay line-based digital PWM pulse generator of the type shown in FIG. 2, an associated timing diagram for which is presented in FIG. 3. As shown therein, an Integer PWM Pulse that encompasses a prescribed number P of clock cycles of a reference clock signal CLOCK is applied to a multistage tapped delay line 200 containing a plurality of cascaded delay stages 200-1, 200-2, . . . , 200-N (each of which may be comprised of a pair of (MOSFET) inverter stages). Each delay stage corresponds to the minimum time resolution or granularity by which the Integer PWM Pulse may be adjusted. The delay of each of the delay stages 200-j is a specific fraction of the CLOCK signal period from which the Integer PWM pulse was constructed as an integer number P of CLOCK cycles. Ideally, for N stages of delay, each stage should provide a delay of 1/(N+1) of the CLOCK signal period.
The output of each delay stage is coupled to a respective input of an N+1:1 signal selector 210, the output of which is coupled to one input of an OR gate 220. A second input of the OR gate 220 is coupled to receive the Integer PWM Pulse. Thus, OR gate 220 will logically OR the Integer PWM Pulse with the output of whichever delay stage 200-j is selected in accordance with a fractional delay select signal coupled to the select input 212 of signal selector 210.
Depending upon the fractional delay Di imparted by each delay stage, and depending upon which jth one of its inputs is selected, signal selector 210 will produce a version of the Integer PWM Pulse delayed by jxDi referred to as the Delayed Integer PWM Pulse. Logically ORing the Integer PWM Pulse and the Delayed Integer PWM Pulse produces a Non-Integer PWM Pulse having a front edge (e.g., rising edge) 301 that is coincident with the front edge (e.g., rising edge) 311 of the Integer PWM Pulse and a termination (e.g., falling edge) 302 that is coincident with the termination (e.g., falling edge) 312 of the Delayed Integer PWM Pulse.
Now although the fractional delay scheme of FIG. 2 provides a potentially effective solution to the PWM digital resolution problem, it is limited by practical considerations, such as differences among fabrication runs of its integrated circuit manufacturing process, and operational variations, such as changes in temperature and supply voltage.
In accordance with the present invention, shortcomings of conventional approaches for generating a fractional clock pulse signal for a PWM pulse generator are effectively obviated by a tapped delay line-based, fractional clock pulse generator, operational parameters of which are adjusted as necessary to maintain a desired fractional precision of the duty-cycle of a generated PWM clock pulse signal. Pursuant to a first, phase locked loop (PLL)-based embodiment of the invention, the tapped delay line-based digital PWM pulse generator of FIG. 2 is augmented to include a compensating phase locked-loop, that is formed around an auxiliary tapped delay line used to implement a voltage controlled oscillator of the PLL. In accordance with a second embodiment of the invention, the PWM pulse generator is configured as a xe2x80x98pseudo PLLxe2x80x99-type, open-loop tapped delay line architecture.
In the first (PLL) embodiment, represented in FIG. 4, one or more parameters of the respective stages of an auxiliary, multistage, delay line-configured ring oscillator have a predetermined relationship with respect to those of the PWM tapped delay line, based upon desired operating conditions of the PWM pulse generator, as well as desired performance of the PLL, whereby parameters of the delay stages of the auxiliary, multistage delay line of the PLL are appropriately correlated with those of the PWM tapped delay line. As a result, a common operational adjustment parameter (e.g., delay stage bias voltage) is able to produce slightly different delays in the two respective delay lines having a prescribed correlation by design.
Any phase error between a reference clock signal CLOCK and the xe2x80x98clockxe2x80x99 signal generated by the multistage, delay line-configured ring oscillator causes a bias control unit to adjust the bias voltage applied to both delay lines. Since the respective delays imparted by the delay line stages of the auxiliary, multistage delay line of the PLL""s ring oscillator are appropriately correlated with those of the delay stages of the PWM tapped pulse delay line, then whatever adjustment is carried out by the PLL bias control to lock its multistage delay line ring oscillator (VCO) to the reference clock signal will produce a corresponding adjustment of the individual delays of the delay line stages of the PWM pulse generator. This produces a high precision fractional adjustment of the duty-cycle of the PWM pulse produced by the output OR gate that is effectively independent of processing variations and operational parameters such as temperature and supply voltage.
In the open-loop xe2x80x98pseudo PLLxe2x80x99-type tapped delay line architecture of the second embodiment, represented in FIG. 5 and associated with the timing diagram in FIG. 6, the Integer PWM Pulse is applied to the input of a multistage tapped delay line, the number of stages of which determines the resolution, or granularity, to which the system clock signal will be divided, and nominally encompasses one cycle of the system clock signal. The Integer PWM Pulse is also input to a register delay that imparts a single system clock period delay to the Integer PWM Pulse producing the Unity Delayed Integer PWM Pulse. The Unity Delayed Integer PWM Pulse and the output of the Nth delay stage are coupled the inputs of a phase detector, the output of which is coupled to a delay stage adjustment circuit such as a bias voltage generator. No delay stage of the tapped delay line has its output fed back to the delay line input stage, so that the second embodiment may be considered an open-loop xe2x80x98pseudo PLLxe2x80x99-type tapped delay line.
The input (or simply a logic 0 signal) and the first Nxe2x88x921 outputs of the N delay stages of the multistage delay line are coupled to respective inputs of an N:1 signal selector whose output is coupled to an OR gate, as in the first embodiment. A second input of the OR gate is coupled to receive the Integer PWM Pulse. As in the first embodiment, the OR gate logically OR""s the Integer PWM Pulse with the output of a selected delay stage of the delay line. The output of the OR gate produces the Non-Integer PWM Pulse whose leading edge is coincident with the leading edge of the Integer PWM Pulse and whose trailing edge is coincident with the trailing edge of the output of the selected delay stage.
As in the first embodiment, the output of the phase detector provides a phase error signal that is used to adjust the operation of each of the delay stages of the tapped delay line. In the second embodiment, however, rather than being referenced to the high frequency digital system clock, as in the first embodiment, the phase detector is referenced to the Unity Delayed Integer PWM Pulse that derived from the Integer PWM Pulse supplied directly to the delay line. The duration of the PWM output pulse is thereby determined by the delay granularity imparted by a respective one of the delay line stages and from which delay line stage output the Delayed Integer PWM Pulse signal is derived.
In operation, phase error between the Unity Delayed Integer PWM Pulse and the N stage delayed Integer PWM Pulse signal will cause the bias control unit to adjust its output or bias voltage. As this bias voltage is coupled to each of the delay stages of the tapped delay line, the amount of delay imparted by each delay stage will be appropriately adjusted, so that the intended fractional clock delay adjustment of the duty-cycle of the Integer PWM Pulse signal will be maintained effectively independent of processing variations and operational parameters.